Generate
A concurrent statement used to create regular structures or conditional
structures during elaboration.
Syntax
Label: for ParameterName in Range generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
Label: if Condition generate
[Declarations...
begin]
ConcurrentStatements...
end generate [Label];
Where
architecture-begin--end
block-begin--end
generate-begin--end
Rules
The Range and Condition must both be static, i.e. they cannot include signals.
Things to remember
The Label at the beginning of the generate statement cannot be omitted.
Synthesis
Synthesis is straightforward, but not all synthesis tools support generate!
Tips
For...generate is useful to replace repeated instances of the same
component.
In VHDL'87 a generate statement cannot contain declarations. To include
declarations in a generate you would have to nest a block statement.
Example
G1: for I in 1 to Depth generate
L: BLK port map (A(I), B(I+1)); -- Repeated instance
end generate G1;
G2: if Option = TRUE generate
process -- Optional process
begin
...
end process;
end generate;
See Also
Concurrent Statement, For Loop, If, Range
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